Programmable integrated circuits (e.g., a field programmable gate array (FPGA), programmable logic device (PLD)) can contain a packet network structure known as a network on a chip (NoC) which is programmed using a network referred to herein as a NoC configuration network (NCN). The NCN includes multiple switches which route packets between configurable logic. To do so, the NCN assigns unique addresses to the ports coupled to the configuration memories. However, assigning addresses is time consuming. Moreover, the configuration of the NCN can change depending on the configuration of the programmable integrated circuit which means the addresses assigned to one NCN will not work in a programmable integrated circuit with a different construction.